1. Field of the Invention
The present invention relates to a semiconductor memory device and method for multiplexing write data thereof. More specifically, the present invention relates to a semiconductor memory device and method for multiplexing write data thereof, wherein write data input through a DQ pad are multiplexed in front of a write driving unit of a memory core region.
2. Discussion of Related Art
DRAMs are classified into X4, X8 and X16 according to data widths, and fabrication using different packages. Generally, however, since X4, X8 and X16 are designed at once, the DRAMs operate differently depending upon X4, X and X16. In the case of X16, sixteen data bits are input/output. In the case of X8, eight data bits are input/output. In the case of X4, only four data bits are input/output.
Therefore, even in the case of the same global I/O bus GIO, not only data input to different pads DQ are transmitted to a memory core region depending upon X4, X8 and X16 at the time of a write operation, but also data output from a memory cell are output to different pads DQ even in the case of the same global I/O bus and even upon read operation.
Furthermore, the prefetch concept has emerged while the DRAM shifts from a SDR DRAM to a DDR DRAM. In the DDR SDRAM, 2-bit data are accessed from a memory cell every clock cycle and are then output to a data pad, which is called 2-bit prefetch. In a DDR2 SDRAM, 4-bit data are accessed from a memory cell every clock cycle and are then output to a data pad, which is called 4-bit prefetch. In a DDR3 SDRAM, 8-bit data are accessed from a memory cell every clock cycle and are then output to a data pad, which is called 8-bit prefetch.
For example, in a DDR2 SDRAM, if a data width is X16, the DDR2 SDRAM is 4-bit prefetch. Thus, 4*16=64 data bits are moved with the DRAM at the same time.
FIG. 1 is a block diagram showing a write path being a data input path among a data I/O path.
Referring to FIG. 1, DQ pads DQ<0:15> receive write data to be written into memory cells (not shown) form the outside upon a write operation. Sixteen write data bits output from the DQ pads DQ<0:15> are transmitted to a global I/O bus GIO through an input buffer 100, a write latch unit 200, a write multiplexer unit 300 and a data amplifier unit 400. At this time, the write multiplexer unit 300 is disposed between the data amplifier unit 400 and the write latch unit 200, and multiplexes the write data received from the write latch unit 200 and then transmits the multiplexed write data to the data amplifier unit 400. The data amplifier unit 400 selects only data that will be written into memory cells (not shown) according to a highest row address (ROW<12>; 256 Mb DDR2 SDRAM) and a column address COL<11>, and sends the selected data to the global I/O bus GIO. A write driving unit 500 drives the write data received from the global I/O bus GIO, and then sends them to local I/O buses LIO and LIOB.
FIGS. 2 to 6 show paths along which write data U<0:7> and L<0:7> received through the DQ pads and the write latch unit 200 are multiplexed in the write multiplexer unit 300, and are then transmitted to the data amplifier unit 400.
Referring to FIGS. 2 to 6, the DQ pad receives the write data U<0:7> and L<0:7> from the outside and then outputs them. The write latch unit 200 consists of sixteen write latch circuits UDQ<0:7> and LDQ<0:7>. The write multiplexer unit 300 includes sixteen write multiplexers 301 to 316. The data amplifier unit 400 has sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7>.
FIG. 2 is a block diagram showing the operation of the write multiplexer unit 300 when a data width is X4.
In the case where the data width is X4, the write multiplexers 301 to 316 multiplex four write data bits L<0:3> output from the write latch circuits LDQ<0:3> into 16, and then send the multiplexed write data to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7>, respectively.
The operation in which the write multiplexers 301 to 316 multiplex the four write data bits L<0:3> output from the write latch circuits LDQ<0:3> into 16, and then send the multiplexed write data to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7>, respectively, will now be described in detail with reference to FIG. 2 and FIGS. 6A to 6P.
First, if the write data bits L<0> transmitted to the write latch circuit LDQ<0> are input to the write multiplexer 308 shown in FIG. 6H, and a transfer gate TG22 is thus turned on according to a signal X4, the write data L<0> is transmitted to the data I/O sense amplifier USA<7> through a first metal line (a data line 300-11 composed of metal 1), a second metal line (a data line 310-1 compose of metal 2), and a first metal line 300-1. Further, if the write data bits L<0> are also input to the write multiplexer 301 shown in FIG. 6A and a transfer gate TG1 is thus turned on according to the signal X4, the write data bits L<0> are sent to the data I/O sense amplifier USA<0> through the first metal line 300-11, a second metal line 310-4 and a first metal line 300-4. If the write data L<0> are input to the write multiplexer 316 shown in FIG. 6P, and a transfer gate TG39 is thus turned on according to the signal X4, the write data bits L<0> are transmitted to the sense amplifier LSA<7> through the first metal line 300-11, the second metal line 310-10 and the first metal line 300-10. If the write data bits L<0> are input to the write multiplexer 309 shown in FIG. 6I, and a transfer gate TG25 is thus turned on according to the signal X4, the write data bits L<0> are directly transmitted to the data I/O sense amplifier LSA<7> through the first metal line 300-11.
Second, if the write data bits L<1> transmitted to the write latch circuit LDQ<1> are input to the write multiplexers 307, 302, 315, 310 shown in FIGS. 6G, 6B, 6O and 6J, respectively, and transfer gates TG19, TG4, TG37 and TG27 are respectively turned on according to the signal X4, in the same manner as the first method, the write data bits L<1> are transmitted to the data I/O sense amplifiers USA<6>, USA<1> and LSA<6> and LSA<1>, respectively, through the first metal line 300-12, the second metal lines 310-2, 310-3, 310-9, and the first metal lines 300-2, 300-3 and 300-9.
Third, if the write data bits L<2> transmitted to the write latch circuit LDQ<2> are input to the write multiplexers 303, 305, 311, 313 shown in FIGS. 6C, 6E, 6K and 6M, respectively, and transfer gates TG7, TG11, TG29 and TG32 are respectively turned on according to the signal X4, in the same manner as the first method, the write data L<2> are transmitted to the data I/O sense amplifiers USA<2>, USA<4> and LSA<2> and LSA<4>, respectively, through the first metal line 300-14, the second metal lines 310-6, 310-8, 310-12, and the first metal lines 300-6, 300-8 and 300-16.
Fourth, if the write data bits L<3> transmitted to the write latch circuit LDQ<3> are input to the write multiplexers 304, 306, 312, 314 shown in FIGS. 6D, 6F, 6L and 6N, respectively, and transfer gates TG9, TG15, TG30 and TG35 are respectively turned on according to the signal X4, in the same manner as the first method, the write data L<3> are transmitted to the data I/O sense amplifiers USA<3>, USA<5> and LSA<3> and LSA<5>, respectively, through the first metal line 300-13, the second metal lines 310-5, 310-7, 310-11, and the first metal lines 300-5, 300-7 and 300-15.
As described above, the write data bits L<0:3> transmitted to the write latch circuits LDQ<0:3> are transmitted to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7> through the sixteen first metal lines 300-1 to 300-16 and the twelve second metal lines 310-1 to 310-12.
Then, the data amplifier unit 400 selects only four data from the sixteen write data according to the highest row address ROW<12> and the column address COL<11>, which have information indicating into which memory cell the data will be written, and sends them to the four global I/O buses GIO_L<0:3>.
FIG. 3 is a block diagram showing the operation of the write multiplexer unit 300 when a data width is X8.
In the case where the data width is X8, the write multiplexer 300 multiplexes eight write data bits L<0:7> output from the write latch circuits LDQ<0:7> into 16, and then sends the multiplexed write data to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7>, respectively.
The operation in which the write multiplexer 300 multiplexes eight write data bits L<0:7> output from the write latch circuits LDQ<0:7> into 16, and then sends the multiplexed write data to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7>, respectively, will now be described in detail with reference to FIG. 3 and FIGS. 6A to 6P.
First, if the write data bits L<0> transmitted to the write latch circuit LDQ<0> are input to the write multiplexers 301, 309 shown in FIGS. 6A, 61, and the transfer gates TG1, TG25 are thus turned on, respectively, according to the signal X8, the write data L<0> is transmitted to the data I/O sense amplifiers USA<0>, USA<7> through the first metal line 300-11, the second metal line 310-4, and the first metal line 300-4.
Second, if the write data bits L<1> transmitted to the write latch circuit LDQ<1> are input to the write multiplexers 302, 310 shown in FIGS. 6B and 6J, respectively, and the transfer gates TG4, TG27 are respectively turned on according to the signal X8, the write data L<1> are transmitted to the data I/O sense amplifiers USA<1> and LSA<1>, respectively, through the first metal line 300-12, the second metal line 310-3, and the first metal line 300-3.
Third, if the write data bits L<2> transmitted to the write latch circuit LDQ<2> are input to the write multiplexers 303, 311 shown in FIGS. 6C, 6K, respectively, and the transfer gates TG7, TG29 are respectively turned on according to the signal X8, the write data bits L<2> are transmitted to the data I/O sense amplifiers USA<2> and LSA<2>, respectively, through the first metal line 300-14, the second metal line 310-6, and the first metal line 300-6.
Fourth, if the write data bits L<3> transmitted to the write latch circuit LDQ<3> are input to the write multiplexers 304, 312 shown in FIGS. 6D, 6L, respectively, and the transfer gates TG9, TG30 are respectively turned on according to the signal X8, the write data bits L<3> are transmitted to the data I/O sense amplifiers USA<3> and LSA<3>, respectively, through the first metal line 300-13, the second metal line 310-5, and the first metal line 300-5.
Fifth, if the write data bits L<4> transmitted to the write latch circuit LDQ<4> are input to the write multiplexers 305, 311 shown in FIGS. 6E, 6M, respectively, and the transfer gates TG12, TG31 are respectively turned on according to the signal X8, the write data bits L<4> are transmitted to the data I/O sense amplifiers USA<4> and LSA<4>, respectively, through the first metal line 300-16, the second metal line 310-16, and the first metal line 300-8.
Sixth, if the write data bits L<5> transmitted to the write latch circuit LDQ<5> are input to the write multiplexers 306, 314 shown in FIGS. 6F, 6N, respectively, and the transfer gates TG16, TG34 are respectively turned on according to the signal X8, the write data bits L<5> are transmitted to the data I/O sense amplifiers USA<5> and LSA<5>, respectively, through the first metal line 300-15, the second metal line 310-15, and the first metal line 300-7.
Seventh, if the write data bits L<6> transmitted to the write latch circuit LDQ<6> are input to the write multiplexers 307, 315 shown in FIGS. 6G, 60, respectively, and the transfer gates TG20, TG38 are respectively turned on according to the signal X8, the write data bits L<6> are transmitted to the data I/O sense amplifiers USA<6> and LSA<6>, respectively, through the first metal line 300-9, the second metal line 310-14, and the first metal line 300-2.
Eighth, if the write data bits L<7> transmitted to the write latch circuit LDQ<7> are input to the write multiplexers 308, 316 shown in FIGS. 6H, 6P, respectively, and the transfer gates TG23, TG40 are respectively turned on according to the signal X8, the write data bits L<7> are transmitted to the data I/O sense amplifiers USA<7> and LSA<7>, respectively, through the first metal line 300-10, the second metal line 310-13, and the first metal line 300-1.
As described above, the write data bits L<0:7> transmitted to the write latch circuits LDQ<0:7> are transmitted to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7> through the sixteen first metal lines 300-1 to 300-16 and the eighth second metal lines 310-3 to 310-6, 310-13 to 310-16.
Then, the data amplifier unit 400 selects only eight of the sixteen write data according to the highest row address ROW<12>, which has information indicating into which memory cell the data will be written, and sends the selected eight data to the eight global I/O buses GIO_L<0:7>.
FIG. 4 is a block diagram showing the operation of the write multiplexer unit 300 when a data width is X16.
In the case where the data width is X16, the sixteen write data bits U<0:7> and L<0:7> output from the write latch circuits UDQ<0:7> and LDQ0:7> are transmitted to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7>, which correspond to each other one to one.
The operation in which the write multiplexers 301 to 316 multiplex the sixteen write data bits U<0:7> and L<0:7> output from the write latch circuits UDQ<0:7> and LDQ<0:7> into 16, and then send the multiplexed write data to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7>, respectively, will now be described in detail with reference to FIG. 4 and FIGS. 6A to 6P.
If the write data bits U<0:7> and L<0:7> transmitted to the write latch circuits UDQ<0:7> and LDQ<0:7> are input to the write multiplexers 301 to 316 shown in FIGS. 6A to 6P, and the transfer gates TG2, TG5, TG8, TG10, TG13, TG17, TG21, TG24, TG25, TG27, TG29, TG30, TG31, TG34, TG38 and TG40 are turned on according to a X16 signal, the write data bits U<0:7> and L<0:7> are transmitted to the data I/O sense amplifiers USA<0:7, LSA<0:7> through the first metal lines 300-1 to 300-16.
At this time, the write latch circuits UDQ<0:7> and LDQ<0:7> correspond to the sixteen first metal lines 300-1 to 300-16 one to one. The sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7> also correspond to the sixteen first metal lines 300-1 to 300-16 one to one.
As described above, the sixteen write data bits U<0:7> and L<0:7> transmitted to the write latch circuits UDQ<0:7> and LDQ<0:7> are transmitted to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7> through the sixteen first metal lines 300-1 to 300-16. Then, the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7> transmit the sixteen write data bits U<0:7> and L<0:7> to the sixteen global I/O buses GIO_U<0:7> and GIO_L<0:7>.
FIG. 5 is a block diagram showing a path along which the write data bits U<0:7> and L<0:7> are transmitted to the sixteen data I/O sense amplifiers USA<0:7> and LSA<0:7> through the sixteen first metal lines 300-1 to 300-16, and the sixteen second metal lines 310-1 to 310-16 shown in FIGS. 2 to 4.
However, the eighth second metal lines 310-17 to 310-24, which are not provided in FIGS. 2 to 4, are provided in FIG. 5. The reason why the eighth second metal lines 310-17 to 310-24 are provided in FIG. 5 is for transmitting the four write data bits L<0:3> transmitted to the write latch circuit LDQ<0:3> to the sixteen sense amplifiers USA<0:7> and LSA<0:7> through the eighth second metal lines 310-17 to 310-24 in test mode TM.
As described above, in order to transmit the sixteen write data bits U<0:7> and L<0:7>, a total of the twenty-four second metal lines 310-1 to 310-24 and the sixteen first metal lines 300-1 to 300-16 inclusive of the test mode TM are needed.
Since the DDR2 DRAM is 4-bit prefetch, however, a 4*24=96 number of second metal lines are needed. Since the DDR3 DRAM is 8-bit prefetch, a 8*24=192 number of second metal lines are required. Accordingly, assuming that a pitch between the second metal lines is 2 μm, the second metal lines of the DDR2 DRAM occupy the area as much as 2 μm*96 in number=192 μm. The second metal lines of the DDR3 DRAM occupy the area as much as 2 μm*192 in numvber=384 μm.
That is, in the prior art, as the number of prefetch increases, the number of the second metal lines needed to multiplex write data abruptly increases. Thus, there is a problem in that the layout and chip size in the peripheral region of a memory device are significantly large.
Furthermore, in the prior art, in the case where the data width is X4, the four data bits L<0:3> are latched in the write latch units LDQ<0:3> latch, and are then transmitted to the data I/O sense amplifiers USA<0:7> and LSA<0:7> through the write multiplexers 301 to 316. In this process, some write data are applied to the data I/O sense amplifier located at the same located as the I/O pad, and some write data are applied to the data I/O sense amplifier after being transmitted to the second metal lines. As such, since the time when the write data arrive at the data I/O sense amplifier becomes different, there is a problem in that skew occurs between data.